Today's computing platforms and processing systems are moving toward an I/O interconnect topology that provides a single communication path between each peripheral device and the host. These computing platforms and processing systems may use packetized communications for communicating between the switching elements within the tree structure. Examples of such computing platforms and processing systems include what is referred to as, for example, peripheral component interconnect (PCI) systems and PCI Express systems. Peripheral devices are discovered by such platforms and systems through an enumeration process performed by a host system element.
A problem with these platforms and systems is that because of their hierarchical tree structure, only one communication path exists between any peripheral device and the host requiring the host to participate in all communications. This is inefficient especially when peripherals are capable of direct communication therebetween. In addition, system performance can decrease when any particular communication path is overloaded. Furthermore, if any communication path fails, no redundant path is available.
Thus, there is a general need for an improved computing platform and processing system. Thus, there is also a general need for an improved method of communication with peripherals devices. There is also a need for a system and method that provides shorter communication paths between peripheral devices. There is also a need for a system and method that allows peripherals to communicate directly without host intervention. There is also a need for a system and method that allows peripherals to identify other peripherals by a memory mapped I/O address. There is also a need for a system and method that discovers inter-hierarchical and/or intra-hierarchical communication paths between switching elements of host systems.